id: MTQ3Nzg3IDEyMQ

reference: 147787

documentId: 22429611

connectionPointId: 121

lastModificationDate: 1535445840307

Jobbtitel: Senior Verification Engineer

Arbetsbeskrivning:
Education and Qualifications Master’s degree in Electrical, Electronic, Computer or Software Engineering, Applied Physics or other relevant technical disciplines Skills and Experience You have thorough knowledge of SystemVerilog for verification of complex design IP You have significant experience of architecting and implementing functional verification environments for complex IP and developing re-usable and scalable code. You have knowledge of UVM and deep understanding of formal methods and strong scripting skills (UNIX shell scripting, Python or Perl, TCL, etc.) – being able to develop scripting and infrastructure to support new flows. You have ability to quickly understand and apply complex specification details and willingness to tackle varied and complex technical challenges You like working and communicating with remote design centres and have strong communication skills, ability to work well as part of a team Desirable Experience of emulation flows and FPGA Experience and track record of formal methods Knowledge of C/C++/SystemC Experience of verifying low power designs in a mixed signal environment Experience of analogue/ mixed signal verification Experience and track record of digital design - ideally SystemC, SystemVerilog Experience of digital implementation and DFT The role covers digital design and development activities focused on verification of Arm’s digital IP in a low power, mixed signal environment. You will play a key role in defining and implementing the verification strategies to ensure our IP is robust and high quality and conforms to the relevant quality, performance and functionality requirements and standards. Job Requirements: You will require a proven track record and experience of digital verification in a suitably complex verification environment as well as being comfortable with standard directed tests. You will have utilised common digital verification techniques such as constrained-random, UVM, formal methods etc. You will be comfortable using SystemVerilog to develop verification components and be familiar with the tools and processes for developing test benches and completing all aspects of the verification process. You must be comfortable developing verification flows to make best use of EDA tools and resources available. With offices around the world, Arm is a diverse organisation of dedicated, innovative and highly talented professionals. By enabling a vibrant, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we inspire our people to share their unique contributions to Arm's success in the global marketplace

numberOfPosts: 2

jobCategoriesCodes_0: http://data.europa.eu/esco/isco/C2511

jobCategoriesCodes_1: http://data.europa.eu/esco/isco/C2512

jobCategoriesCodes_2: http://data.europa.eu/esco/isco/C2513

jobCategoriesCodes_3: http://data.europa.eu/esco/isco/C2514

jobCategoriesCodes_4: http://data.europa.eu/esco/isco/C2521

abstractJV_contact_0:
Link to the vacancy on the Swedish job board

positionTypeCode: directhire

contractTypeCodes_0: fulltime

Arbetsgivare Namn: Arm Sweden AB

source: PES-SWEDEN